This invention relates to circuits and methods for generating multi-phase clock signals. More particularly, this invention relates to circuits and methods for generating multi-phase clock signals using hierarchical delays.
Circuits that generate multi-phase clock signals typically output a plurality of clock signals phase-shifted in equally-spaced increments relative to a reference clock signal. The output clock signals typically have the same frequency as the reference clock signal. For example, a typical circuit may output four clock signals phase-shifted by 90°, 180°, 270° and 360°, respectively, relative to the reference clock signal. Circuits that generate multi-phase clock signals are often used, for example, in electronic systems having complex timing requirements in which multi-function operations are completed during a single reference clock cycle. Multi-phase clock signals are also used in electronic systems in which an operation extends over more than one reference clock cycle.
Conventional circuits generate multi-phase clock signals using analog voltage-controlled delay units (VCDs). The phase shifts (i.e., time delays) generated by the VCDs are adjustable and can be controlled by adjusting the supply voltage. VCDs typically require the use of analog charge pumps and loop filters. It is well-known that analog designs are more difficult to mass produce reliably within stated specifications and are less portable to various process technologies than digital designs.
In view of the foregoing, it would be desirable to provide circuits and methods for generating multi-phase clock signals that rely less on analog components and more on digital components.